• Status Unconfirmed
  • Percent Complete
  • Ticket Type Bug Report
  • Category
  • Assigned To No-one
  • Operating System All
  • Severity Critical
  • Priority Normal
  • Reported Version 1.10
  • Due in Version Undecided
  • Due Date Undecided
  • Votes 0
  • Private No
Attached to Project: EmBitz IDE
Opened by dietervolke (dietervolke) - 2017-08-24

Ticket#284 - F4xx JTAG-DP GPIO blocking

PB3,PB4,PA15 pins are locked in ALT mode suggesting debug interface is Full SWJ (JTAG-DP + SW-DP).
JTAG pins permanently mapped to these therefore it's not possible to use MODER to switch pins to GEN mode.

After reset these pins are 0x2 (AF) if a pin are set in user software to 0x1 (GEN) after compile the pin
is strangely enough 0x3 (Analog). PB3 and PB4 pins can be made into GEN mode by stopping the
debugger then change the registers manually to 0x1 then run the debug session from where you stopped

This ticket does not depend on any other tickets.