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  How to combine 192 kb and 64 kb ram ?
Posted by: makem - 02-03-2018, 04:17 PM - Forum: STmicro - Replies (2)

Hi 
I have this error.

Thanks!

||bin\Debug\429zit6.elf section `.bss' will not fit in region `RAM'|
||region RAM overflowed with stack|
||region `RAM' overflowed by 29780 bytes|
||=== Build finished: 3 errors, 0 warnings (0 minutes, 10 seconds) ===|


/*------------------------------------------------------------------------------
* Linker script for running in internal SRAM on the STM32F429ZI
*-------------------------------stm32f429zi_flash.ld---------------------------------------------*/

OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)

/* Memory Spaces Definitions */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
CCRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
}

/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/


SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)

KEEP(*(.init))
KEEP(*(.fini))

/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)

/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)

*(.rodata*)
KEEP(*(.eh_frame*))
} > RAM

.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > RAM

__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > RAM
__exidx_end = .;

__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)

. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);

. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);


. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);

. = ALIGN(4);
/* All data end */
__data_end__ = .;

} > RAM
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM

.heap (NOLOAD):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM

/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(8);
*(.stack)
} > RAM

/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);

/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}


/*------------------------------------------------------------------------------
* Linker script for running in internal SRAM on the STM32F429ZI
*--------------------stm32f429zi_sram.ld---------------------------*/

OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)

/* Memory Spaces Definitions */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
CCRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
}

/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/


SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)

KEEP(*(.init))
KEEP(*(.fini))

/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)

/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)

*(.rodata*)
KEEP(*(.eh_frame*))
} > RAM

.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > RAM

__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > RAM
__exidx_end = .;

__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)

. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);

. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);


. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);

. = ALIGN(4);
/* All data end */
__data_end__ = .;

} > RAM
.bss (NOLOAD):
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM

.heap (NOLOAD):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM

/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(8);
*(.stack)
} > RAM

/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);

/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}


/* Cortex-M4 stm32f429x.S*/
.syntax unified
.arch armv7-m

.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop

.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0xC00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit

.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */


// External Interrupts
.long WWDG_IRQHandler // Window WatchDog
.long PVD_IRQHandler // PVD through EXTI Line detection
.long TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EXTI line
.long RTC_WKUP_IRQHandler // RTC Wakeup through the EXTI line
.long FLASH_IRQHandler // FLASH
.long RCC_IRQHandler // RCC
.long EXTI0_IRQHandler // EXTI Line0
.long EXTI1_IRQHandler // EXTI Line1
.long EXTI2_IRQHandler // EXTI Line2
.long EXTI3_IRQHandler // EXTI Line3
.long EXTI4_IRQHandler // EXTI Line4
.long DMA1_Stream0_IRQHandler // DMA1 Stream 0
.long DMA1_Stream1_IRQHandler // DMA1 Stream 1
.long DMA1_Stream2_IRQHandler // DMA1 Stream 2
.long DMA1_Stream3_IRQHandler // DMA1 Stream 3
.long DMA1_Stream4_IRQHandler // DMA1 Stream 4
.long DMA1_Stream5_IRQHandler // DMA1 Stream 5
.long DMA1_Stream6_IRQHandler // DMA1 Stream 6
.long ADC_IRQHandler // ADC1, ADC2 and ADC3s
.long CAN1_TX_IRQHandler // CAN1 TX
.long CAN1_RX0_IRQHandler // CAN1 RX0
.long CAN1_RX1_IRQHandler // CAN1 RX1
.long CAN1_SCE_IRQHandler // CAN1 SCE
.long EXTI9_5_IRQHandler // External Line[9:5]s
.long TIM1_BRK_TIM9_IRQHandler // TIM1 Break and TIM9
.long TIM1_UP_TIM10_IRQHandler // TIM1 Update and TIM10
.long TIM1_TRG_COM_TIM11_IRQHandler // TIM1 Trigger and Commutation and TIM11
.long TIM1_CC_IRQHandler // TIM1 Capture Compare
.long TIM2_IRQHandler // TIM2
.long TIM3_IRQHandler // TIM3
.long TIM4_IRQHandler // TIM4
.long I2C1_EV_IRQHandler // I2C1 Event
.long I2C1_ER_IRQHandler // I2C1 Error
.long I2C2_EV_IRQHandler // I2C2 Event
.long I2C2_ER_IRQHandler // I2C2 Error
.long SPI1_IRQHandler // SPI1
.long SPI2_IRQHandler // SPI2
.long USART1_IRQHandler // USART1
.long USART2_IRQHandler // USART2
.long USART3_IRQHandler // USART3
.long EXTI15_10_IRQHandler // External Line[15:10]s
.long RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EXTI Line
.long OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EXTI line
.long TIM8_BRK_TIM12_IRQHandler // TIM8 Break and TIM12
.long TIM8_UP_TIM13_IRQHandler // TIM8 Update and TIM13
.long TIM8_TRG_COM_TIM14_IRQHandler // TIM8 Trigger and Commutation and TIM14
.long TIM8_CC_IRQHandler // TIM8 Capture Compare
.long DMA1_Stream7_IRQHandler // DMA1 Stream7
.long FMC_IRQHandler // FMC
.long SDIO_IRQHandler // SDIO
.long TIM5_IRQHandler // TIM5
.long SPI3_IRQHandler // SPI3
.long UART4_IRQHandler // UART4
.long UART5_IRQHandler // UART5
.long TIM6_DAC_IRQHandler // TIM6 and DAC1&2 underrun errors
.long TIM7_IRQHandler // TIM7
.long DMA2_Stream0_IRQHandler // DMA2 Stream 0
.long DMA2_Stream1_IRQHandler // DMA2 Stream 1
.long DMA2_Stream2_IRQHandler // DMA2 Stream 2
.long DMA2_Stream3_IRQHandler // DMA2 Stream 3
.long DMA2_Stream4_IRQHandler // DMA2 Stream 4
.long ETH_IRQHandler // Ethernet
.long ETH_WKUP_IRQHandler // Ethernet Wakeup through EXTI line
.long CAN2_TX_IRQHandler // CAN2 TX
.long CAN2_RX0_IRQHandler // CAN2 RX0
.long CAN2_RX1_IRQHandler // CAN2 RX1
.long CAN2_SCE_IRQHandler // CAN2 SCE
.long OTG_FS_IRQHandler // USB OTG FS
.long DMA2_Stream5_IRQHandler // DMA2 Stream 5
.long DMA2_Stream6_IRQHandler // DMA2 Stream 6
.long DMA2_Stream7_IRQHandler // DMA2 Stream 7
.long USART6_IRQHandler // USART6
.long I2C3_EV_IRQHandler // I2C3 event
.long I2C3_ER_IRQHandler // I2C3 error
.long OTG_HS_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out
.long OTG_HS_EP1_IN_IRQHandler // USB OTG HS End Point 1 In
.long OTG_HS_WKUP_IRQHandler // USB OTG HS Wakeup through EXTI
.long OTG_HS_IRQHandler // USB OTG HS
.long DCMI_IRQHandler // DCMI
.long CRYP_IRQHandler // CRYP crypto
.long HASH_RNG_IRQHandler // Hash and Rng
.long FPU_IRQHandler // FPU
.long UART7_IRQHandler // UART7
.long UART8_IRQHandler // UART8
.long SPI4_IRQHandler // SPI4
.long SPI5_IRQHandler // SPI5
.long SPI6_IRQHandler // SPI6
.long SAI1_IRQHandler // SAI1
.long LTDC_IRQHandler // LTDC
.long LTDC_ER_IRQHandler // LTDC error
.long DMA2D_IRQHandler // DMA2D

.size __isr_vector, . - __isr_vector
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */

ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__

#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.flash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .flash_to_ram_loop
#else
subs r3, r2
ble .flash_to_ram_loop_end
.flash_to_ram_loop:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .flash_to_ram_loop
.flash_to_ram_loop_end:
#endif

#ifndef __NO_SYSTEM_INIT
ldr r0, =SystemInit
blx r0
#endif

ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler

/* Our weak _start alternative if we don't use the library _start
* The zero init section must be cleared, otherwise the librtary is
* doing that */
.align 1
.thumb_func
.weak _start
.type _start, %function
_start:

/* Zero fill the bss segment. */
ldr r1, = __bss_start__
ldr r2, = __bss_end__
movs r3, #0
b .fill_zero_bss
.loop_zero_bss:
str r3, [r1], #4

.fill_zero_bss:
cmp r1, r2
bcc .loop_zero_bss

/* Jump to our main */
bl main
b .
.size _start, . - _start

/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm

def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler Default_Handler

// External Interrupts
def_irq_handler WWDG_IRQHandler // Window WatchDog
def_irq_handler PVD_IRQHandler // PVD through EXTI Line detection
def_irq_handler TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EXTI line
def_irq_handler RTC_WKUP_IRQHandler // RTC Wakeup through the EXTI line
def_irq_handler FLASH_IRQHandler // FLASH
def_irq_handler RCC_IRQHandler // RCC
def_irq_handler EXTI0_IRQHandler // EXTI Line0
def_irq_handler EXTI1_IRQHandler // EXTI Line1
def_irq_handler EXTI2_IRQHandler // EXTI Line2
def_irq_handler EXTI3_IRQHandler // EXTI Line3
def_irq_handler EXTI4_IRQHandler // EXTI Line4
def_irq_handler DMA1_Stream0_IRQHandler // DMA1 Stream 0
def_irq_handler DMA1_Stream1_IRQHandler // DMA1 Stream 1
def_irq_handler DMA1_Stream2_IRQHandler // DMA1 Stream 2
def_irq_handler DMA1_Stream3_IRQHandler // DMA1 Stream 3
def_irq_handler DMA1_Stream4_IRQHandler // DMA1 Stream 4
def_irq_handler DMA1_Stream5_IRQHandler // DMA1 Stream 5
def_irq_handler DMA1_Stream6_IRQHandler // DMA1 Stream 6
def_irq_handler ADC_IRQHandler // ADC1, ADC2 and ADC3s
def_irq_handler CAN1_TX_IRQHandler // CAN1 TX
def_irq_handler CAN1_RX0_IRQHandler // CAN1 RX0
def_irq_handler CAN1_RX1_IRQHandler // CAN1 RX1
def_irq_handler CAN1_SCE_IRQHandler // CAN1 SCE
def_irq_handler EXTI9_5_IRQHandler // External Line[9:5]s
def_irq_handler TIM1_BRK_TIM9_IRQHandler // TIM1 Break and TIM9
def_irq_handler TIM1_UP_TIM10_IRQHandler // TIM1 Update and TIM10
def_irq_handler TIM1_TRG_COM_TIM11_IRQHandler // TIM1 Trigger and Commutation and TIM11
def_irq_handler TIM1_CC_IRQHandler // TIM1 Capture Compare
def_irq_handler TIM2_IRQHandler // TIM2
def_irq_handler TIM3_IRQHandler // TIM3
def_irq_handler TIM4_IRQHandler // TIM4
def_irq_handler I2C1_EV_IRQHandler // I2C1 Event
def_irq_handler I2C1_ER_IRQHandler // I2C1 Error
def_irq_handler I2C2_EV_IRQHandler // I2C2 Event
def_irq_handler I2C2_ER_IRQHandler // I2C2 Error
def_irq_handler SPI1_IRQHandler // SPI1
def_irq_handler SPI2_IRQHandler // SPI2
def_irq_handler USART1_IRQHandler // USART1
def_irq_handler USART2_IRQHandler // USART2
def_irq_handler USART3_IRQHandler // USART3
def_irq_handler EXTI15_10_IRQHandler // External Line[15:10]s
def_irq_handler RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EXTI Line
def_irq_handler OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EXTI line
def_irq_handler TIM8_BRK_TIM12_IRQHandler // TIM8 Break and TIM12
def_irq_handler TIM8_UP_TIM13_IRQHandler // TIM8 Update and TIM13
def_irq_handler TIM8_TRG_COM_TIM14_IRQHandler // TIM8 Trigger and Commutation and TIM14
def_irq_handler TIM8_CC_IRQHandler // TIM8 Capture Compare
def_irq_handler DMA1_Stream7_IRQHandler // DMA1 Stream7
def_irq_handler FMC_IRQHandler // FMC
def_irq_handler SDIO_IRQHandler // SDIO
def_irq_handler TIM5_IRQHandler // TIM5
def_irq_handler SPI3_IRQHandler // SPI3
def_irq_handler UART4_IRQHandler // UART4
def_irq_handler UART5_IRQHandler // UART5
def_irq_handler TIM6_DAC_IRQHandler // TIM6 and DAC1&2 underrun errors
def_irq_handler TIM7_IRQHandler // TIM7
def_irq_handler DMA2_Stream0_IRQHandler // DMA2 Stream 0
def_irq_handler DMA2_Stream1_IRQHandler // DMA2 Stream 1
def_irq_handler DMA2_Stream2_IRQHandler // DMA2 Stream 2
def_irq_handler DMA2_Stream3_IRQHandler // DMA2 Stream 3
def_irq_handler DMA2_Stream4_IRQHandler // DMA2 Stream 4
def_irq_handler ETH_IRQHandler // Ethernet
def_irq_handler ETH_WKUP_IRQHandler // Ethernet Wakeup through EXTI line
def_irq_handler CAN2_TX_IRQHandler // CAN2 TX
def_irq_handler CAN2_RX0_IRQHandler // CAN2 RX0
def_irq_handler CAN2_RX1_IRQHandler // CAN2 RX1
def_irq_handler CAN2_SCE_IRQHandler // CAN2 SCE
def_irq_handler OTG_FS_IRQHandler // USB OTG FS
def_irq_handler DMA2_Stream5_IRQHandler // DMA2 Stream 5
def_irq_handler DMA2_Stream6_IRQHandler // DMA2 Stream 6
def_irq_handler DMA2_Stream7_IRQHandler // DMA2 Stream 7
def_irq_handler USART6_IRQHandler // USART6
def_irq_handler I2C3_EV_IRQHandler // I2C3 event
def_irq_handler I2C3_ER_IRQHandler // I2C3 error
def_irq_handler OTG_HS_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out
def_irq_handler OTG_HS_EP1_IN_IRQHandler // USB OTG HS End Point 1 In
def_irq_handler OTG_HS_WKUP_IRQHandler // USB OTG HS Wakeup through EXTI
def_irq_handler OTG_HS_IRQHandler // USB OTG HS
def_irq_handler DCMI_IRQHandler // DCMI
def_irq_handler CRYP_IRQHandler // CRYP crypto
def_irq_handler HASH_RNG_IRQHandler // Hash and Rng
def_irq_handler FPU_IRQHandler // FPU
def_irq_handler UART7_IRQHandler // UART7
def_irq_handler UART8_IRQHandler // UART8
def_irq_handler SPI4_IRQHandler // SPI4
def_irq_handler SPI5_IRQHandler // SPI5
def_irq_handler SPI6_IRQHandler // SPI6
def_irq_handler SAI1_IRQHandler // SAI1
def_irq_handler LTDC_IRQHandler // LTDC
def_irq_handler LTDC_ER_IRQHandler // LTDC error
def_irq_handler DMA2D_IRQHandler // DMA2D

.end

Print this item

  Linker ignores implementation of function
Posted by: Traubensaft - 28-02-2018, 05:20 PM - Forum: ArmGCC - EmBlocks - Replies (4)

Hi,

I am using emBitz with CubeMX generated HAL code. In HAL, interrupt handling callback functions are pre-implemented with a __weak symbol. The developer is supposed to write his own implementeation in the user files (e.g. main.c)

In my case I made a custum implementation of void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) in main.c but the linker does not use my implementation to "overwrite" the __weak function of the HAL.

How do I have to configure emBitz to get things working?

Thank you in advance
~Traubensaft

Print this item

  Sys register selected viewing?
Posted by: dietervolke - 20-02-2018, 04:14 AM - Forum: EmBitz IDE - Replies (1)

I need to look at a group of system registers from various sources not affiliated with each other in one assembled group, is it possible somehow to mark these registers and collect them into a window?

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  STM32f10x -- ADS1115 -- I2C
Posted by: Mohammad Affash - 09-02-2018, 09:06 AM - Forum: STmicro - Replies (4)

hello guys ,

i have a problem with the communication between STM32F103 and ADS1115 i have a very simple code ,which just establisch the connect but i always have the AF Flag set ...
in the datasheet of ADS1115 the address is 1001000 when the ADDR pin is connected to GND and so it is in my case and one bit   left shift means 10010000=0x90 .
now when i generate start bit and then send the address the AF goes to "1" Acknowledge failure and thats mean the address doesnt match !!!
any help would be appreciated .
this is the code :

Code:
#include "stm32f10x_conf.h"
#define ADS1115_Address  0x90

int main(void){
      GPIO_InitTypeDef GPIO_InitStructure;
     I2C_InitTypeDef I2C_InitStructure;
   



     RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
     RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);

     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
     GPIO_Init(GPIOB, &GPIO_InitStructure);

     GPIO_PinRemapConfig(GPIO_Remap_I2C1, ENABLE);

     I2C_DeInit(I2C1);

     I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
     I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
     I2C_InitStructure.I2C_ClockSpeed = 100000;
     I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
     I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
     I2C_InitStructure.I2C_OwnAddress1 = 0;
     I2C_Init(I2C1, &I2C_InitStructure);
      I2C_Cmd(I2C1, ENABLE);

            I2C_GenerateSTART(I2C1,ENABLE);
           
           I2C_Send7bitAddress(I2C1,0x90,I2C_Direction_Transmitter);
}

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  Hardfault in startup
Posted by: Mohammad Affash - 05-02-2018, 03:57 PM - Forum: EmBitz IDE - Replies (4)

hi guys ..
im kind of beginner and i have a problem .. i'm using STM32f10x und trying to make simple communication between the MCU and ADS1115 using i2c ..
when i try to debug the programm never enter the main because in startup file a Hardfault happens i couldnt know why is this happening.

this is the startup code :

Code:
/* File: startup_ARMCM3.S
* Purpose: startup file for Cortex-M3 devices. Should use with
*   GCC for ARM Embedded Processors
* Version: V1.3
* Date: 08 Feb 2012
*
* Copyright (c) 2012, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
   * Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   * Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   * Neither the name of the ARM Limited nor the
     names of its contributors may be used to endorse or promote products
     derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES//
* LOSS OF USE, DATA, OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
   .syntax unified
   .arch armv7-m

   .section .stack
   .align 3
#ifdef __STACK_SIZE
   .equ    Stack_Size, __STACK_SIZE
#else
   .equ    Stack_Size, 0x400
#endif
   .globl    __StackTop
   .globl    __StackLimit
__StackLimit:
   .space    Stack_Size
   .size __StackLimit, . - __StackLimit
__StackTop:
   .size __StackTop, . - __StackTop

   .section .heap
   .align 3
#ifdef __HEAP_SIZE
   .equ    Heap_Size, __HEAP_SIZE
#else
   .equ    Heap_Size, 0xC00
#endif
   .globl    __HeapBase
   .globl    __HeapLimit
__HeapBase:
   .if    Heap_Size
   .space    Heap_Size
   .endif
   .size __HeapBase, . - __HeapBase
__HeapLimit:
   .size __HeapLimit, . - __HeapLimit

   .section .isr_vector
   .align 2
   .globl __isr_vector
__isr_vector:
   .long    __StackTop            /* Top of Stack */
   .long    Reset_Handler         /* Reset Handler */
   .long    NMI_Handler           /* NMI Handler */
   .long    HardFault_Handler     /* Hard Fault Handler */
   .long    MemManage_Handler     /* MPU Fault Handler */
   .long    BusFault_Handler      /* Bus Fault Handler */
   .long    UsageFault_Handler    /* Usage Fault Handler */
   .long    0                     /* Reserved */
   .long    0                     /* Reserved */
   .long    0                     /* Reserved */
   .long    0                     /* Reserved */
   .long    SVC_Handler           /* SVCall Handler */
   .long    DebugMon_Handler      /* Debug Monitor Handler */
   .long    0                     /* Reserved */
   .long    PendSV_Handler        /* PendSV Handler */
   .long    SysTick_Handler       /* SysTick Handler */

               // External Interrupts
   .long    WWDG_IRQHandler            // Window Watchdog
   .long    PVD_IRQHandler             // PVD through EXTI Line detect
   .long    TAMPER_IRQHandler          // Tamper
   .long    RTC_IRQHandler             // RTC
   .long    FLASH_IRQHandler           // Flash
   .long    RCC_IRQHandler             // RCC
   .long    EXTI0_IRQHandler           // EXTI Line 0
   .long    EXTI1_IRQHandler           // EXTI Line 1
   .long    EXTI2_IRQHandler           // EXTI Line 2
   .long    EXTI3_IRQHandler           // EXTI Line 3
   .long    EXTI4_IRQHandler           // EXTI Line 4
   .long    DMA1_Channel1_IRQHandler   // DMA1 Channel 1
   .long    DMA1_Channel2_IRQHandler   // DMA1 Channel 2
   .long    DMA1_Channel3_IRQHandler   // DMA1 Channel 3
   .long    DMA1_Channel4_IRQHandler   // DMA1 Channel 4
   .long    DMA1_Channel5_IRQHandler   // DMA1 Channel 5
   .long    DMA1_Channel6_IRQHandler   // DMA1 Channel 6
   .long    DMA1_Channel7_IRQHandler   // DMA1 Channel 7
   .long    ADC1_2_IRQHandler          // ADC1_2
   .long    USB_HP_CAN1_TX_IRQHandler  // USB High Priority or CAN1 TX
   .long    USB_LP_CAN1_RX0_IRQHandler // USB Low  Priority or CAN1 RX0
   .long    CAN1_RX1_IRQHandler        // CAN1 RX1
   .long    CAN1_SCE_IRQHandler        // CAN1 SCE
   .long    EXTI9_5_IRQHandler         // EXTI Line 9..5
   .long    TIM1_BRK_IRQHandler        // TIM1 Break
   .long    TIM1_UP_IRQHandler         // TIM1 Update
   .long    TIM1_TRG_COM_IRQHandler    // TIM1 Trigger and Commutation
   .long    TIM1_CC_IRQHandler         // TIM1 Capture Compare
   .long    TIM2_IRQHandler            // TIM2
   .long    TIM3_IRQHandler            // TIM3
   .long    TIM4_IRQHandler            // TIM4
   .long    I2C1_EV_IRQHandler         // I2C1 Event
   .long    I2C1_ER_IRQHandler         // I2C1 Error
   .long    I2C2_EV_IRQHandler         // I2C2 Event
   .long    I2C2_ER_IRQHandler         // I2C2 Error
   .long    SPI1_IRQHandler            // SPI1
   .long    SPI2_IRQHandler            // SPI2
   .long    USART1_IRQHandler          // USART1
   .long    USART2_IRQHandler          // USART2
   .long    USART3_IRQHandler          // USART3
   .long    EXTI15_10_IRQHandler       // EXTI Line 15..10
   .long    RTCAlarm_IRQHandler        // RTC Alarm through EXTI Line
   .long    USBWakeUp_IRQHandler       // USB Wakeup from suspend

   .size    __isr_vector, . - __isr_vector

   .text
   .thumb
   .thumb_func
   .align 2
   .globl    Reset_Handler
   .type    Reset_Handler, %function
Reset_Handler:
/*     Loop to copy data from read only memory to RAM. The ranges
*      of copy from/to are specified by following symbols evaluated in
*      linker script.
*      __etext: End of code section, i.e., begin of data sections to copy from.
*      __data_start__/__data_end__: RAM address range that data should be
*      copied to. Both must be aligned to 4 bytes boundary.  */

    ldr    r1, =__etext
   ldr    r2, =__data_start__
   ldr    r3, =__data_end__

#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.flash_to_ram_loop:
   cmp     r2, r3
   ittt    lt
   ldrlt   r0, [r1], #4
   strlt   r0, [r2], #4
   blt    .flash_to_ram_loop
#else
   subs    r3, r2
   ble    .flash_to_ram_loop_end
.flash_to_ram_loop:
   subs    r3, #4
   ldr    r0, [r1, r3]
   str    r0, [r2, r3]
   bgt    .flash_to_ram_loop
.flash_to_ram_loop_end:
#endif

#ifndef __NO_SYSTEM_INIT
   ldr    r0, =SystemInit
   blx    r0
#endif

   ldr    r0, =_start
   bx    r0
   .pool
   .size Reset_Handler, . - Reset_Handler

/* Our weak _start alternative if we don't use the library _start
* The zero init section must be cleared, otherwise the librtary is
* doing that */
   .align 1
   .thumb_func
   .weak _start
   .type _start, %function
_start:

   /* Zero fill the bss segment. */
   ldr   r1, = __bss_start__
   ldr   r2, = __bss_end__
   movs  r3, #0
   b  .fill_zero_bss
.loop_zero_bss:
   str  r3, [r1], #4

.fill_zero_bss:
   cmp  r1, r2
   bcc  .loop_zero_bss

   /* Jump to our main */
   bl main
   b .
   .size    _start, . - _start

/*    Macro to define default handlers. Default handler
*    will be weak symbol and just dead loops. They can be
*    overwritten by other handlers */
   .macro    def_irq_handler    handler_name
   .align 1
   .thumb_func
   .weak    \handler_name
   .type    \handler_name, %function
\handler_name :
   b    .
   .size    \handler_name, . - \handler_name
   .endm

   def_irq_handler    NMI_Handler
   def_irq_handler    HardFault_Handler
   def_irq_handler    MemManage_Handler
   def_irq_handler    BusFault_Handler
   def_irq_handler    UsageFault_Handler
   def_irq_handler    SVC_Handler
   def_irq_handler    DebugMon_Handler
   def_irq_handler    PendSV_Handler
   def_irq_handler    SysTick_Handler
   def_irq_handler    Default_Handler

               // External Interrupts
   def_irq_handler    WWDG_IRQHandler            // Window Watchdog
   def_irq_handler    PVD_IRQHandler             // PVD through EXTI Line detect
   def_irq_handler    TAMPER_IRQHandler          // Tamper
   def_irq_handler    RTC_IRQHandler             // RTC
   def_irq_handler    FLASH_IRQHandler           // Flash
   def_irq_handler    RCC_IRQHandler             // RCC
   def_irq_handler    EXTI0_IRQHandler           // EXTI Line 0
   def_irq_handler    EXTI1_IRQHandler           // EXTI Line 1
   def_irq_handler    EXTI2_IRQHandler           // EXTI Line 2
   def_irq_handler    EXTI3_IRQHandler           // EXTI Line 3
   def_irq_handler    EXTI4_IRQHandler           // EXTI Line 4
   def_irq_handler    DMA1_Channel1_IRQHandler   // DMA1 Channel 1
   def_irq_handler    DMA1_Channel2_IRQHandler   // DMA1 Channel 2
   def_irq_handler    DMA1_Channel3_IRQHandler   // DMA1 Channel 3
   def_irq_handler    DMA1_Channel4_IRQHandler   // DMA1 Channel 4
   def_irq_handler    DMA1_Channel5_IRQHandler   // DMA1 Channel 5
   def_irq_handler    DMA1_Channel6_IRQHandler   // DMA1 Channel 6
   def_irq_handler    DMA1_Channel7_IRQHandler   // DMA1 Channel 7
   def_irq_handler    ADC1_2_IRQHandler          // ADC1_2
   def_irq_handler    USB_HP_CAN1_TX_IRQHandler  // USB High Priority or CAN1 TX
   def_irq_handler    USB_LP_CAN1_RX0_IRQHandler // USB Low  Priority or CAN1 RX0
   def_irq_handler    CAN1_RX1_IRQHandler        // CAN1 RX1
   def_irq_handler    CAN1_SCE_IRQHandler        // CAN1 SCE
   def_irq_handler    EXTI9_5_IRQHandler         // EXTI Line 9..5
   def_irq_handler    TIM1_BRK_IRQHandler        // TIM1 Break
   def_irq_handler    TIM1_UP_IRQHandler         // TIM1 Update
   def_irq_handler    TIM1_TRG_COM_IRQHandler    // TIM1 Trigger and Commutation
   def_irq_handler    TIM1_CC_IRQHandler         // TIM1 Capture Compare
   def_irq_handler    TIM2_IRQHandler            // TIM2
   def_irq_handler    TIM3_IRQHandler            // TIM3
   def_irq_handler    TIM4_IRQHandler            // TIM4
   def_irq_handler    I2C1_EV_IRQHandler         // I2C1 Event
   def_irq_handler    I2C1_ER_IRQHandler         // I2C1 Error
   def_irq_handler    I2C2_EV_IRQHandler         // I2C2 Event
   def_irq_handler    I2C2_ER_IRQHandler         // I2C2 Error
   def_irq_handler    SPI1_IRQHandler            // SPI1
   def_irq_handler    SPI2_IRQHandler            // SPI2
   def_irq_handler    USART1_IRQHandler          // USART1
   def_irq_handler    USART2_IRQHandler          // USART2
   def_irq_handler    USART3_IRQHandler          // USART3
   def_irq_handler    EXTI15_10_IRQHandler       // EXTI Line 15..10
   def_irq_handler    RTCAlarm_IRQHandler        // RTC Alarm through EXTI Line
   def_irq_handler    USBWakeUp_IRQHandler       // USB Wakeup from suspend

   .end

after these two lines
Code:
#ifndef __NO_SYSTEM_INIT
   ldr    r0, =SystemInit
   blx    r0
#endif


the function SystemInit() will be called and before the debbuger do any step inside this function a Hardfault happens.


this is my code in c :
Code:
/*
**
**                           Main.c
**
**
**********************************************************************/
/*
  Last committed:     $Revision: 00 $
  Last changed by:    $Author: $
  Last changed date:  $Date:  $
  ID:                 $Id:  $ https://dam.sygr.de/repos/projekte/27674_systack/trunk/PT/

**********************************************************************/
#include "stm32f10x_conf.h"


#define ADS1115_Address  0x48 // bei ADS1115 Pin3 wird mit GND angeschlossen ,das entspricht der Adresse 0b1001000 = 0x48.
#define ADS_Config_Reg_Add 0x01 // die Adresse vom Konfiguration Register bei ADS1115.
#define MSB_Config_Reg     0xE0 // Konfiguration siehe Datasheet.
#define LSB_Config_Reg     0x00 // Konfiguration siehe Datasheet.
volatile uint8_t dataByte1;
volatile uint8_t dataByte0;
volatile uint8_t receivedDataByte1;
volatile uint8_t receivedDataByte0;
volatile uint8_t i2cDirectionWrite;
volatile uint8_t i2cByteCounter;
volatile uint8_t i2cBusyFlag;

void I2CInit() {  //  I2C Initialisierung


     GPIO_InitTypeDef GPIO_InitStructure;
     I2C_InitTypeDef I2C_InitStructure;
     NVIC_InitTypeDef NVIC_InitStructure;

       SystemInit();

     RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
     RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);

     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
     GPIO_Init(GPIOB, &GPIO_InitStructure);

     GPIO_PinRemapConfig(GPIO_Remap_I2C1, ENABLE);

     NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn;
     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
     NVIC_Init(&NVIC_InitStructure);

     NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
     NVIC_Init(&NVIC_InitStructure);

     I2C_DeInit(I2C1);

     I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
     I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
     I2C_InitStructure.I2C_ClockSpeed = 100000;
     I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
     I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
     I2C_InitStructure.I2C_OwnAddress1 = 0;
     I2C_Init(I2C1, &I2C_InitStructure);

     I2C_ITConfig(I2C1, I2C_IT_EVT, ENABLE);
     I2C_ITConfig(I2C1, I2C_IT_BUF, ENABLE);
     I2C_ITConfig(I2C1, I2C_IT_ERR, ENABLE);

     I2C_Cmd(I2C1, ENABLE);

              }

void I2C1_EV_IRQHandler(void){


   if(I2C_GetFlagStatus(I2C1, I2C_FLAG_SB) == SET){
   if(i2cDirectionWrite){
     // STM32 Transmitter
     I2C_Send7bitAddress(I2C1, ADS1115_Address, I2C_Direction_Transmitter);
   }else{
     // STM32 Receiver
     I2C_Send7bitAddress(I2C1, ADS1115_Address, I2C_Direction_Receiver);
   }
 }else if(I2C_GetFlagStatus(I2C1, I2C_FLAG_ADDR) == SET || I2C_GetFlagStatus(I2C1, I2C_FLAG_BTF) == SET){
   I2C_ReadRegister(I2C1, I2C_Register_SR1);
   I2C_ReadRegister(I2C1, I2C_Register_SR2);
   if(i2cDirectionWrite){
     // STM32 Transmitter
     if(i2cByteCounter == 2){
       I2C_SendData(I2C1, dataByte1);
       i2cByteCounter--;
     }else if(i2cByteCounter == 1){
       I2C_SendData(I2C1, dataByte0);
       i2cByteCounter--;
     }else{
       I2C_GenerateSTOP(I2C1, ENABLE);
       i2cBusyFlag = 0;
     }
   }
 }else if(I2C_GetFlagStatus(I2C1, I2C_FLAG_RXNE) == SET){
   // STM32 Receiver
    I2C_SendData(I2C1, dataByte1);
   I2C_ReadRegister(I2C1, I2C_Register_SR1);
   I2C_ReadRegister(I2C1, I2C_Register_SR2);
   i2cByteCounter--;
   if(i2cByteCounter == 1){
     I2C_AcknowledgeConfig(I2C1, DISABLE);
     I2C_GenerateSTOP(I2C1, ENABLE);
     receivedDataByte1 = I2C_ReceiveData(I2C1);
   }else{
     receivedDataByte0 = I2C_ReceiveData(I2C1);
     i2cBusyFlag = 0;
   }
 }



}

void I2C1_ER_IRQHandler(void){
 I2C_GenerateSTOP(I2C1, ENABLE);
 i2cBusyFlag = 0;

 I2C_ClearFlag(I2C1, I2C_FLAG_AF);
 I2C_ClearFlag(I2C1, I2C_FLAG_ARLO);
 I2C_ClearFlag(I2C1, I2C_FLAG_BERR);
}




uint16_t i2c_getData(void){

      return (receivedDataByte1 << 8) | receivedDataByte0;

                       }

void i2c_writeByte(uint8_t byte){

    while(i2cBusyFlag){};
    while(I2C_GetFlagStatus(I2C1,I2C_FLAG_BUSY)){};
    dataByte0 = byte;
    i2cDirectionWrite = 1;
    i2cBusyFlag = 1;
    i2cByteCounter = 1;
    I2C_GenerateSTART(I2C1, ENABLE);

    }

void i2c_writeTwoBytes(uint8_t byte1, uint8_t byte0){
    while(i2cBusyFlag){};
    while(I2C_GetFlagStatus(I2C1,I2C_FLAG_BUSY)){};
    dataByte1 = byte1;
    dataByte0 = byte0;
    i2cDirectionWrite = 1;
    i2cBusyFlag = 1;
    i2cByteCounter = 2;
    I2C_GenerateSTART(I2C1, ENABLE);


                }

void i2c_readTwoBytes(){
   while(i2cBusyFlag){};
   while(I2C_GetFlagStatus(I2C1,I2C_FLAG_BUSY)){};
   i2cDirectionWrite = 0;
   i2cBusyFlag = 1;
   i2cByteCounter = 2;
   I2C_AcknowledgeConfig(I2C1, ENABLE);
   I2C_GenerateSTART(I2C1, ENABLE);

              }

void ADS_init(){    //  ADS Initialisierung

   i2c_writeByte(ADS_Config_Reg_Add);
   i2c_writeTwoBytes(LSB_Config_Reg,MSB_Config_Reg);


           }


int main(void){
     I2CInit();
     ADS_init();

     while(1){
     i2c_readTwoBytes();
     uint16_t data  = i2c_getData();
             }

}

Thank u

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  Download/Debugging Silabs BLue Gecko BGM111
Posted by: vierling - 02-02-2018, 04:16 PM - Forum: Debug interface scripting - Replies (4)

Hi,

I have "imported" a BGM111-Project from Simplicity Studio 4 to EmBitz.
It compiles/linked without any Errors.

When I start Debugging the J-Link-Interface opens.
My init-String is "-select USB -device BGM111 -if SWD -speed auto -noir"
The J-Link supports the BGM111-Modul/MCU
the gdb-server is: C:\Program Files (x86)\SEGGER\JLink_V630a\JLinkGDBServer.exe

Unfortunately the Download not starts.
the J-Link connect to the Target (Silabs EFR32BG1B232F256GM48)
read 4 Bytes (Register?) and thats all...

What's wrong.

EmBitz is much more faster/better than Simplicity Studio.

Kind regards
Thomas



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  EB Monitor and Semihosting poorly explained
Posted by: Bitscrambler - 02-02-2018, 10:59 AM - Forum: Examples - Replies (3)

We are using the EMBitz IDE and are satisfied with the standard options.
But the debugging features "Semihosting" and "EBmon" are not working as expected.
A simple "Hello World" example with stdio.h include file doesn`t show any output on both options (Semihosting/EBMon).
F.e. the semihosting flag is set in the menues.
Can somebody list the preferences necassery to use that features ? (What are living variables ? How to declare ?).
Are there any manuals ?
If possible give us a step by step explanation or an example.


Thank you very much.

Bitscrambler

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  OnHalt Script
Posted by: jrvanho - 29-01-2018, 03:37 PM - Forum: Debug interface scripting - Replies (2)

Is it possible to have the IDE/Debugger call a script to toggle an LED/modify registers on a halt of the debugger?

I am looking for something similar to IAR's "execUserExecutionStopped()"
http://www.testech-elect.com/percepio/tr...bench.html

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  Could not debug with ST-Link
Posted by: vargham - 23-01-2018, 07:42 AM - Forum: STmicro - Replies (5)

I use EmBitz with STM32 devices daily since 2016. The debug was fine until today. The bundled STLinkGDB.exe could not connect to the debugger. I tried a few ST-Links with all USB ports, restart Windows, reinstall ST-Link driver and utility. No luck. The same setup works fine with ST-Link utility software.
I tried to start STLinkGDB.exe manually. Here is the error message:
C:\Program Files (x86)\STMicroelectronics\stlink_server>cd "C:\Program Files (x86)\EmBitz\1.11\share\contrib"
C:\Program Files (x86)\EmBitz\1.11\share\contrib>STLinkGDB.exe
STLINK GDB Server (EmBitz Dec  8 2016 12:12:38)
Connect under reset is active.
2018-01-23T07:31:57 WARN E:\_stlink\stlink-master\src\stlink-usb.c: Couldn't open STlink/V2 probe at 002:008

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Bug STM32F105 project creation problem
Posted by: AlexNL - 10-01-2018, 05:32 PM - Forum: EmBitz IDE - Replies (3)

Hello. It's very strangely but when i create project for STM32 connectivity line device (like stm32f103) i have compilation error:
Thanks.



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